View MAX9675_1655209.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ________________________________________________________________ maxim integrated products 1 out0 out1 out15 in0 cameras in1 in15 monitor monitor monitor MAX9675 MAX9675 16 x 16 switch matrix power-on reset serial interface thermal shutdown decode logic disable all outputs latches 256 16 16 matrix register 96 bits update register 16 bits enable/disable a v * a v * a v * a v * *a v = +1v/v or +2v/v a0?3 mode in0 in1 in2 in15 din sclk update ce reset out0 out1 out2 out15 v cc v ee dgnd v dd dout aout agnd typical operating circuit functional diagram 19-4230; rev 0; 7/08 spi and qspi are trademarks of motorola, inc. general description the MAX9675 is a nonblocking 16 x 16 video cross- point switch with buffered inputs and outputs. the device operates on ?v analog supplies. digital logic is supplied separately from an independent +2.7v to +5v supply. the MAX9675 inputs and outputs are buffered with all outputs able to drive a standard 75 reverse- terminated video load. the switching matrix and programmable gain are con- trolled through an spi/qspi-compatible 3-wire seri- al interface. the serial interface is designed to operate in either of two modes to provide fast updates and ini- tialization. all outputs are held in the disabled state during power-up to avoid signal conflicts in large switching arrays. the programmability and high level of integration make the MAX9675 an ideal choice for nonblocking video switch arrays in security, surveillance, and video- on-demand systems. the MAX9675 is available in a 100-pin tqfp package and specified over the extended -40? to +85? tem- perature range. applications security systems video routing video-on-demand systems features ? 16 x 16 nonblocking matrix with buffered inputs and outputs ? operates at ?v supply ? individually programmable output buffer gain (a v = +1v/v or +2v/v) ? high-impedance output disable for wired-or connections ? 0.1db gain flatness to 14mhz ? -3db bandwidth 110mhz ? -62db crosstalk, -110db isolation at 6mhz for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package MAX9675ecq+ -40 c to +85 c 100 tqfp pin configuration appears at end of data sheet. +denotes a lead-free/rohs-compliant package. evaluation kit available
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics?ual supplies ?v (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = 0, r l = 150 to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 5) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog supply voltage (v cc - v ee ) .....................................+11v digital supply voltage (v dd - dgnd) ...................................+6v analog supplies to analog ground (v cc - agnd) and (agnd - v ee ) ......................................+6v analog ground to digital ground .........................-0.3v to +0.3v in_ voltage range .......................... (v cc + 0.3v) to (v ee - 0.3v) out_ short-circuit duration to agnd, v cc , or v ee ......indefinite sclk, ce , update , mode, a_, din, dout, reset , aout .........................(v dd + 0.3v) to (dgnd - 0.3v) current into any analog input pin (in_) ...........................?0ma current into any analog output pin (out_).....................?5ma continuous power dissipation (t a = +70?) 100-pin tqfp (derate 22.2mw/? above +70?).....1777mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? parameter symbol conditions min typ max units operating supply voltage range v cc - v ee guaranteed by psrr test 4.5 10.5 v logic-supply voltage range v dd to dgnd 2.7 5.5 v (v ee + 2.5v) < v in _ < (v cc - 2.5v), a v = +1v/v, r l = 150 1 (v ee + 2.5v) < v in _ < (v cc - 2.5v), a v = +1v/v, r l = 10k 1 (v ee + 3.75v) < v in _ < (v cc - 3.75v), a v = +2v/v, r l = 150 2 (v ee + 3.75v) < v in _ < (v cc - 3.75v), a v = +2v/v, r l = 10k 2 gain (note 1) a v (v ee + 1v) < v in _ < (v cc - 1.2v), a v = +1v/v, r l = 10k 1 v/v r l = 10k 0.5 1.5 gain matching (channel to channel) r l = 150 0.5 2 %
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain _______________________________________________________________________________________ 3 dc electrical characteristics?ual supplies ?v (continued) (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = 0, r l = 150 to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 5) parameter symbol conditions min typ max units temperature coefficient of gain tc av 10 ppm/ c r l = 10k v e e + 1 v c c - 1.2 a v = +1v/v r l = 150 v e e + 2.5 v c c - 2.5 r l = 10k v e e + 3 v c c - 3.1 input voltage range v in _ a v = +2v/v r l = 150 v e e + 3.75 v c c - 3.75 v r l = 10k v e e + 1 v c c - 1.2 v output voltage range v out r l = 150 v e e + 2.5 v c c - 2.5 v input bias current i b 4 11 ? input resistance r in _ (v ee + 1v) < v in _ < (v cc - 1.2v) 10 m a v = +1v/v ? ?0 output offset voltage v offset a v = +2v/v ?0 ?0 mv output short-circuit current i sc sinking or sourcing, r l = 1 ?0 ma enabled output impedance z out (v ee + 1v) < v in _ < (v cc - 1.2v) 0.2 output leakage current, disable mode i od (v ee + 1v) < v out _ < (v cc - 1.2v) 0.004 1 ? dc power-supply rejection ratio psrr 4.5v < (v cc - v ee ) < 10.5v 60 70 db outputs enabled, t a = +25 c 100 150 outputs enabled 175 i cc r l = outputs disabled 55 75 outputs enabled, t a = +25 c 95 150 outputs enabled 175 i ee r l = outputs disabled 50 75 quiescent supply current i dd 4 8 ma
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 4 _______________________________________________________________________________________ logic-level characteristics (v cc = +5v, v ee = -5v, v dd = +2.7v to +5.5v, agnd = dgnd = 0, v in _ = 0, r l = 150 to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (notes 2, 5) parameter symbol conditions min typ max units v dd = +5v 3 input-voltage high level v ih v dd = +3v 2 v v dd = +5v 0.8 input-voltage low level v il v dd = +3v 0.6 v excluding reset -1 +0.01 +1 input current high level i ih v i > 2v reset -30 -20 ? excluding reset -1 +0.01 +1 input current low level i il v i < 1v reset -300 -235 ? i source = 1ma, v dd = +5v 4.7 4.9 output-voltage high level v oh i source = 1ma, v dd = +3v 2.7 2.9 v i sink = 1ma, v dd = +5v 0.1 0.3 output-voltage low level v ol i sink = 1ma, v dd = +3v 0.1 0.3 v v dd = +5v, v o = +4.9v 1 4 output current high level i oh v dd = +3v, v o = +2.7v 1 8 ma v dd = +5v, v o = +0.1v 1 4 output current low level i ol v dd = +3v, v o = +0.3v 1 8 ma ac electrical characteristics?ual supplies ?v (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units a v = +1v/v 110 small-signal -3db bandwidth bw ss v out = 20mv p-p a v = +2v/v 78 mhz a v = +1v/v 80 medium-signal -3db bandwidth bw ms v out _ = 200mv p-p a v = +2v/v 75 mhz a v = +1v/v 40 large-signal -3db bandwidth bw ls v out _ = 2v p-p a v = +2v/v 50 mhz a v = +1v/v 14 small-signal 0.1db bandwidth bw 0.1db-ss v out = 20mv p-p a v = +2v/v 11 mhz a v = +1v/v 14 medium-signal 0.1db bandwidth bw 0.1db-ms v out _ = 200mv p-p a v = +2v/v 11 mhz a v = +1v/v 14 large-signal 0.1db bandwidth bw 0.1db-ls v out _ = 2v p-p a v = +2v/v 11 mhz v out _ = 2v step, a v = +1v/v 150 slew rate sr v out _ = 2v step, a v = +2v/v 150 v/?
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain _______________________________________________________________________________________ 5 ac electrical characteristics?ual supplies ?v (continued) (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = 0, r l = 150 to agnd, a v = +1v/v, and t a = +25?, unless other- wise noted.) parameter symbol conditions min typ max units a v = +1v/v 60 settling time t s 0.1% v out_ = 0 to 2v step a v = +2v/v 60 ns a v = +1v/v 50 switching transient (glitch) (note 3) a v = +2v/v 45 mv f = 100khz 70 ac power-supply rejection ratio f = 1mhz 68 db r l = 1k 0.002 differential gain error (note 4) r l = 150 0.02 % r l = 1k 0.02 differential phase error (note 4) r l = 150 0.12 d eg r ees crosstalk, all hostile f = 6mhz -62 db off-isolation, input to output f = 6mhz -110 db input noise-voltage density e n bw = 6mhz 73 ? rms input capacitance c in 5 pf disabled output capacitance amplifier in disable mode 3 pf capacitive load at 3db output peaking 30 pf output enabled 3 output impedance z out f = 6mhz output disabled 4k
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 6 _______________________________________________________________________________________ switching characteristics (v cc = +5v, v ee = -5v, v dd = +2.7v to +5.5v, dgnd = agnd = 0, v in _ = 0 for dual supplies, r l = 150 to agnd, c l = 100pf, a v = +1v/v, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 5) parameter symbol conditions min typ max units delay: update to video out t pdudvo v in = 0.5v step 200 450 ns delay: update to aout t pdudao mode = 0, time to aout = low after update = low 30 200 ns delay: sclk to dout valid t pddo logic state change in dout on active sclk edge 30 200 ns delay: output disable t pdhoe v out = 0.5v, 1k pulldown to agnd 300 800 ns delay: output enable t pdloe output disabled, 1k pulldown to agnd, v in = 0.5v 200 800 ns setup: ce to sclk t suce 100 ns setup: din to sclk t sudi 100 ns hold time: sclk to din t hddi 100 ns minimum high time: sclk t mnhck 100 ns minimum low time: sclk t mnlck 100 ns minimum low time: update t mnlud 100 ns setup time: update to sclk t suhud rising edge of update to falling edge of sclk 100 ns hold time: sclk to update t hdhud falling edge of sclk to falling edge of update 100 ns setup time: mode to sclk t sumd minimum time from clock edge to mode with valid data clocking 100 ns hold time: mode to sclk t hdmd minimum time from clock edge to mode with valid data clocking 100 ns minimum low time: reset t mnlrst 300 ns delay: reset t pdrst 10k pulldown to agnd, 0.5v step 600 ns note 1: associated output voltage may be determined by multiplying the input voltage by the specified gain (a v ) and adding output offset voltage. note 2: logic-level characteristics apply to the following pins: din, dout, sclk, ce , update , reset , a3?0, mode, and aout . note 3: switching transient settling time is guaranteed by the settling time (t s ) specification. switching transient is a result of updat- ing the switch matrix. note 4: input test signal: 3.58mhz sine wave of amplitude 40ire superimposed on a linear ramp (0 to 100ire). ire is a unit of video-signal amplitude developed by the international radio engineers: 140ire = 1.0v. note 5: all devices are 100% production tested at t a = +25?. specifications over temperature limits are guaranteed by design.
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain _______________________________________________________________________________________ 7 symbol type description ao signal address valid flag ( aout ) ce signal clock enable ( ce ) ck signal clock (sclk) di signal serial-data in (din) do signal serial-data output (dout) md signal mode oe signal output enable rst signal reset input ( reset ) ud signal update vo signal video out (out) h property high- or low-to-high transition hd property hold l property low- or high-to-low transition mn property minimum mx property maximum pd property propagation delay su property setup tr property transition w property width symbol definitions naming conventions all parameters with time units are given a "t" desig- nation, with appropriate subscript modifiers. propagation delays for clocked signals are from the active edge of clock. propagation delay for level-sensitive signals is from input to output at the 50% point of a transition. setup and hold times are measured from the 50% point of signal transition to the 50% point of the clocking signal transition. setup time refers to any signal that must be stable before the active clock edge, even if the signal is not latched or clocked itself. hold time refers to any signal that must be stable during and after active clock edge, even if the sig- nal is not latched or clocked. propagation delays to unobservable internal signals are modified to setup and hold designations applied to observable i/o signals.
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 8 _______________________________________________________________________________________ data and control timing ce: ce di: din do: dout ud: update vo: out_ rst: reset oe: output enable ao: aout t suce t hdce t mnhck t mnlck t sudi t hddi t pddo t hdud t mnlud t suud hi-z t pdudvo t wtrvo t pdudao t pdrstvo t mnlrst t pdhoevo t pdloevo hi-z timing parameter definitions name description t pdudvo delay: update to video out t pdudao delay: update to aout t pddo delay: clk to data out delay: output enable to video output (high: disable) delay: output enable to video output (low: enable) t suce setup: clock enable to clock t sudi setup time: data in to clock timing parameter definitions name description t hddi hold time: clock to data in t mnhck min high time: clk t mnlck min low time: clk t mnlud min low time: update t suhud setup time: update to clk with update high not valid setup time: update to clk with update low t hdhud hold time: clk to update with update high not valid hold time: clk to update with update low t pddido asynchronous delay: data in to data out t mnmd min low time: mode t mxtr max rise time: clk, update t mnlrst min low time: reset t pdrstvo delay: reset to video output ck: sclk t pdhoevo t pdloevo figure 1. timing diagram
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain _______________________________________________________________________________________ 9 typical operating characteristics (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 MAX9675 toc01 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 a v = +2v/v a v = +1v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 MAX9675 toc02 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 MAX9675 toc03 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 MAX9675 toc04 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 MAX9675 toc05 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k a v = +2v/v a v = +1v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 MAX9675 toc06 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k a v = +1v/v a v = +2v/v 0.3 -0.7 0.1 1 10 100 1000 large-signal gain flatness vs. frequency -0.5 MAX9675 toc07 frequency (mhz) normalized gain (db) -0.3 -0.1 0.1 0 -0.2 -0.4 -0.6 0.2 a v = +1v/v a v = +2v/v r l = 150 0.3 -0.7 0.1 1 10 100 1000 large-signal gain flatness vs. frequency -0.5 MAX9675 toc08 frequency (mhz) normalized gain (db) -0.3 -0.1 0.1 0 -0.2 -0.4 -0.6 0.2 a v = +1v/v a v = +2v/v r l = 1k 3 -7 0.1 1 10 100 1000 large-signal frequency response (a v = +1v/v) -5 MAX9675 toc09 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 c l = 30pf c l = 15pf c l = 45pf
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 10 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) 3 -7 0.1 1 10 100 1000 large-signal frequency response (a v = +2v/v) -5 MAX9675 toc10 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 c l = 30pf c l = 15pf c l = 45pf 0.1 10 1 100 1000 medium-signal frequency response (a v = +1v/v) MAX9675 toc11 frequency (mhz) normalized gain (db) -10 -5 5 0 10 15 c l = 45pf c l = 15pf c l = 30pf 7 -3 0.1 1 10 100 1000 medium-signal frequency response (a v = +2v/v) -1 MAX9675 toc12 frequency (mhz) normalized gain (db) 1 3 5 4 2 0 -2 6 c l = 15pf c l = 45pf c l = 30pf -40 -100 0.1 10 100 1 1000 MAX9675 toc13 frequency (mhz) crosstalk (db) -90 -80 -70 -60 -50 crosstalk vs. frequency a v = +1v/v -40 -100 0.1 10 100 1 1000 MAX9675 toc14 frequency (mhz) crosstalk (db) -90 -80 -70 -60 -50 crosstalk vs. frequency a v = +2v/v -10 -100 0.1 100 10 1 distortion vs. frequency -70 -90 -30 -50 0 -60 -80 -20 -40 MAX9675 toc15 frequency (mhz) distortion (dbc) a v = +1v/v 2nd harmonic 3rd harmonic -10 -100 0.1 100 10 1 distortion vs. frequency -70 -90 -30 -50 0 -60 -80 -20 -40 MAX9675 toc16 frequency (mhz) distortion (dbc) a v = +2v/v 2nd harmonic 3rd harmonic 0.1 10 1 100 1000 enabled output impedance vs. frequency MAX9675 toc17 frequency (mhz) output impedance ( ) 1000 -0.1 1 10 100 1m 1 100k 10m 100m 1m 1g MAX9675 toc18 frequency (hz) output impedance ( ) 10 100 1k 10k 100k disabled output impedance vs. frequency
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 11 typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 10m 100m 1m 1g MAX9675 toc19 frequency (hz) off-isolation (db) off-isolation vs. frequency 10k 1m 100k 10m 100m power-supply rejection ratio vs. frequency MAX9675 toc20 frequency (hz) psrr (db) -75 -70 -60 -65 -55 -50 1000 1 10 10k 100k 1m 100 1k 10m input voltage noise vs. frequency 100 MAX9675 toc21 frequency (hz) voltage noise (nv/ hz) 25ns/div large-signal pulse response (a v = +1v/v) input 1v/div output 0.5v/div MAX9675 toc22 25ns/div large-signal pulse response (a v = +2v/v) input 0.5v/div output 0.5v/div MAX9675 toc23 25ns/div medium-signal pulse response (a v = +1v/v) input 100mv/div output 50mv/div MAX9675 toc24 25ns/div medium-signal pulse response (a v = +2v/v) input 50mv/div output 50mv/div MAX9675 toc25 20ns/div switching time (a v = +1v/v) v update 5v/div v out 500mv/div MAX9675 toc26 20ns/div switching time (a v = +2v/v) v update 5v/div v out 1v/div MAX9675 toc27
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 12 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) 20ns/div switching transient (glitch) (a v = +1v/v) v update 5v/div v out 25mv/div MAX9675 toc28 20ns/div switching transient (glitch) (a v = +2v/v) v update 5v/div v out 25mv/div MAX9675 toc29 0 100 50 200 150 250 300 -15 -11 -9 -7 -13 -5 -3 -1 1 3 5 offset voltage distribution MAX9675 toc30 offset voltage (mv) -0.05 0102030405060708090100 0102030405060708090100 differential gain and phase (r l = 150 ) 0 0 -0.02 0.05 0.02 0.04 0.10 0.06 0.08 0.15 ire differential phase ( ) differential gain (%) MAX9675 toc31 0.01 0 0102030405060708090100 0102030405060708090100 differential gain and phase (r l = 1k ) -0.004 0.02 -0.002 0 0.002 0.004 0.03 ire differential gain (%) MAX9675 toc32 -0.01 differential phase ( ) 25ns/div large-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) input 1v/div output 0.5/vdiv MAX9675 toc33 25ns/div large-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) input 0.5v/div output 0.5v/div MAX9675 toc34 25ns/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) input 100mv/div output 50mv/div MAX9675 toc35 25ns/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) input 50mv/div output 50mv/div MAX9675 toc36
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 13 0 20 10 40 30 60 50 70 -50 0 25 -25 50 75 100 supply current vs. temperature MAX9675 toc39 temperature ( c) supply current (ma) i cc i ee i dd typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 to agnd, and t a = +25?, unless otherwise noted.) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -50 0 -25 25 50 75 100 gain vs. temperature MAX9675 toc37 temperature ( c) normalized gain (db) a v = +2v/v a v = +1v/v 1p 10n 1 100p 10p 1n 100n 10 100 MAX9675 toc38 10n 10 1 100n 100 1m 10m 100m 10 1 reset delay (s) c reset (f) reset delay vs. reset capacitance
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 14 ______________________________________________________________________________________ pin description pin name function 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23 in4?n15 buffered analog inputs 2, 4, 6, 8, 10, 12, 14, 16, 45, 46, 82, 83, 84, 91, 93, 95, 97 agnd analog ground 18, 20, 22, 24 a3?0 address programming inputs. connect to dgnd or v dd to select the address for individual output address mode (see table 3). 25, 47, 51, 55, 59, 63, 67, 71, 75, 81 v cc positive analog supply. bypass each pin with a 0.1? capacitor to agnd. connect a single 10? capacitor from one v cc pin to agnd. 26, 27, 38?4, 76, 77, 85?9, 99, 100 n.c. no connection. not internally connected. connect to agnd. 28 dout serial-data output. in complete matrix mode, data is clocked through the 96-bit matrix control shift register. in individual output address mode, data at din passes directly to dout. 29 dgnd digital ground 30 aout address recognition output. aout drives low after successful chip address recognition. 31 sclk serial-clock input 32 ce clock enable input. drive low to enable the serial data interface. 33 mode serial interface mode select input. drive high for complete matrix mode (mode 1) or drive low for individual output address mode (mode 0). 34 reset asynchronous reset input/output. drive reset low to initiate hardware reset. all matrix settings are set to power up defaults and all analog outputs are disabled. additional power-on-reset delay may be set by connecting a small capacitor from reset to dgnd. 35 update update input. drive update low to transfer data from mode registers to the switch matrix. 36 din serial-data input. data is clocked in on the falling edge of sclk. 37 v dd digital logic supply. bypass vdd with a 0.1? capacitor to dgnd. 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 78, 80 out15?ut0 buffered analog outputs. gain is individually programmable for a v = +1v/v or a v = +2v/v through the serial interface. outputs may be individually disabled (high impedance). on power-up, or assertion of reset , all outputs are disabled. 49, 53, 57, 61, 65, 69, 73, 79, 98 v ee negative analog supply. bypass each pin with a 0.1? capacitor to agnd. connect a single 10? capacitor from one v ee pin to agnd. 90, 92, 94, 96 in0?n3 buffered analog inputs
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 15 detailed description the MAX9675 is a highly integrated 16 ? 16 nonblock- ing video crosspoint switch matrix. all inputs and out- puts are buffered, with all outputs able to drive standard 75 reverse-terminated video loads. a 3-wire interface programs the switch matrix and ini- tializes with a single update signal. the unique serial interface operates in one of two modes: complete matrix mode (mode 1) or individual output address mode (mode 0). in the functional diagram, the signal path of the MAX9675 is from the inputs (in0?n15), through the switching matrix, buffered by the output amplifiers, and presented at the output terminals (out0?ut15). the other functional blocks are the serial interface and con- trol logic. each of the functional blocks is described in detail below. analog outputs the MAX9675 outputs are high-speed voltage feedback amplifiers capable of driving 150 (75 back-terminat- ed) loads. the gain, a v = +1v/v or +2v/v, is selectable through programming bit 4 of the serial control word. amplifier compensation is automatically optimized to maximize the bandwidth for each gain selection. each output can be individually enabled and disabled through bit 5 of the serial control word. when disabled, the out- put is high impedance, presenting typically a 4k load, and 3pf output capacitance, allowing multiple outputs to be connected together in building large arrays. on power-up (or asynchronous reset ), all outputs are ini- tialized in the disabled state to avoid output conflicts in large-array configurations. the programming and opera- tion of the MAX9675 is output referred. outputs are con- figured individually to connect to any one of the 16 analog inputs, programmed to the desired gain (a v = +1v/v or +2v/v), or disabled in a high-impedance state. analog inputs the MAX9675 offers 16 analog input channels. each input is buffered before the crosspoint switch matrix, allowing one input to cross-connect to up to 16 outputs. the input buffers are voltage feedback amplifiers with high-input impedance and low-input bias current. this allows the use of very simple input clamp circuits. MAX9675 16 x 16 switch matrix power-on reset serial interface thermal shutdown decode logic disable all outputs latches 256 16 16 matrix register 96 bits update register 16 bits enable/disable a v * a v * a v * a v * *a v = +1v/v or +2v/v a0?3 mode in0 in1 in2 in15 din sclk update ce reset out0 out1 out2 out15 v cc v ee dgnd v dd dout aout agnd functional diagram
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 16 ______________________________________________________________________________________ switch matrix the MAX9675 has 256 individual t-switches making a 16 x 16 switch matrix. the switching matrix is 100% nonblocking, which means that any input may be rout- ed to any output. the switch matrix programming is output referred. each output may be connected to any one of the 16 analog inputs. any one input can be rout- ed to all 16 outputs with no signal degradation. digital interface the digital interface consists of the following pins: din, dout, sclk, aout , update , ce , a3?0, mode, and reset . din is the serial-data input; dout is the serial- data output. sclk is the serial-data clock that clocks data into the data input registers (figure 2). data at din is loaded at each falling edge of sclk. dout is the data shifted out of the 96-bit complete matrix mode (mode = 1). din passes directly to dout when in individual output address mode (mode = 0). the falling edge of update latches the data and pro- grams the matrix. when using individual output address mode, the address recognition output aout drives low when control word bits d13 to d10 match the address programming inputs (a3?0) and update is low. table 1 is the operation truth table. programming the matrix the MAX9675 offers two programming modes: individual output address mode and complete matrix mode. these two distinct programming modes are selected by toggling a single mode pin high or low. both modes operate with the same physical board lay- out. this flexibility allows initial programming of the ic by daisy-chaining and sending one long data word while still being able to address immediately and update individual outputs in the matrix. individual output address mode (mode = 0) drive mode to logic-low to select mode 0. individual outputs are programmed through the serial interface ce update sclk din dout mode aout reset operation/comments 1 x x x x x x 1 no change in logic. 01 d i d i-96 11 1 data at din is clocked on the negative edge of the sclk into the 96-bit complete matrix mode register. dout supplies original data in 96 sclk pulses later. 00xxx111 data in the serial 96-bit complete matrix mode register is transferred into parallel latches that control the switching matrix. 01 d i d i 01 1 data at din is routed to the individual output address mode shift register. din is also connected directly to dout so that all devices on the serial bus may be addressed in parallel. 00xd i d i 00 1 the 4-bit chip address a 3 to a 0 is compared to d 13 to d 10 . if equal, the remaining 10 bits in the individual output address mode register are decoded, allowing reprogramming for a single output. aout signals a successful individual matrix update. x x xxxxx 0 asynchronous reset. all outputs are disabled. other logic remains unchanged. table 1. operation truth table
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 17 with a single 16-bit control word. the control word con- sists of two don? care msbs, the chip address bits, out- put address bits, an output enable/disable bit, an output gain-set bit, and input address bits (tables 2 through 6, and figure 2). in mode 0, data at din passes directly to dout through the data routing gate (figure 3). in this configu- ration, the 16-bit control word is simultaneously sent to all chips in an array of up to 16 addresses. complete matrix mode (mode = 1) drive mode to logic-high to select mode 1. a single 96-bit control word consisting of sixteen 6-bit control words programs all outputs. the 96-bit control word? first 6-bit control word (msbs) programs output 15, and the last 6-bit control word (lsbs) programs output 0 (table 7 and figures 4 and 5). data clocked into the 96-bit complete matrix mode register is latched on the falling edge of update , and the outputs are immedi- ately updated. initialization string the complete matrix mode (mode = 1) is convenient to use to program the matrix at power-up. in a large matrix consisting of many MAX9675 devices, all the devices can be programmed by sending a single bit stream equal to n x 96 bits, where n is the number of MAX9675 devices on the bus. the first 96-bit data word programs the last MAX9675 in line (see the matrix programming section) . bit name function 0 (lsb) input address 0 lsb of input channel select address 1 input address 1 2 input address 2 3 input address 3 msb of input channel select address 4 gain set gain select for output buffer, 0 = gain of +1v/v, 1 = gain of +2v/v 5 output enable enable bit for output, 0 = disable, 1 = enable 6 output address b0 lsb of output buffer address 7 output address b1 8 output address b2 9 output address b3 msb of output buffer address 10 ic address a0 lsb of selected chip address 11 ic address a1 12 ic address a2 13 ic address a3 msb of selected chip address 14 x don? care 15 (msb) x don? care table 2. 16-bit serial control word bit assignments (mode 0: individual output address mode) ic address bit address a3 (msb) a2 a1 a0 (lsb) chip address (hex) chip address (decimal) 0 0 0 0 0h 0 0 0 0 1 1h 1 0 0 1 0 2h 2 0 0 1 1 3h 3 0 1 0 0 4h 4 0 1 0 1 5h 5 0 1 1 0 6h 6 0 1 1 1 7h 7 1 0 0 0 8h 8 1 0 0 1 9h 9 1 0 1 0 ah 10 1 0 1 1 bh 11 1 1 0 0 ch 12 1 1 0 1 dh 13 1 1 1 0 eh 14 1 1 1 1 fh 15 table 3. chip address programming for 16-bit control word (mode 0: individual output address mode)
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 18 ______________________________________________________________________________________ ic address = 5 output address = 3 output (i) enabled, a v = +1v/v, connected to input 12 example of 16-bit serial control word for output control in individual output address mode 16-bit individual output address mode: first 2 bits are don't care bits, last 14 bits clocked into din when mode = 0 create address word; ic address a3?0 is compared to din 13 ?in 10 when update is low; if equal, addressed output is updated. don't care x don't care x output address b3 output address b2 output address b1 output address b0 output enabled gain set = +1v/v input address 3 (msb) = 1 input address 0 (lsb) = 0 input address 2 = 1 input address 1 = 0 ic address a3 ic address a2 ic address a1 ic address a0 update mode sclk din t sumd t hdmd figure 2. mode 0: individual output address mode timing and programming example pin address a3 a2 a1 a0 c h ip a d dr ess ( h ex) c h ip a d dr ess ( d ec im al ) d gnd d gnd d gnd d gnd 0h 0 d gnd d gnd d gnd v d d 1h 1 d gnd d gnd v d d d gnd 2h 2 d gnd d gnd v d d v d d 3h 3 d gnd v d d d gnd d gnd 4h 4 d gnd v d d d gnd v d d 5h 5 d gnd v d d v d d d gnd 6h 6 d gnd v d d v d d v d d 7h 7 v d d d gnd d gnd d gnd 8h 8 v d d d gnd d gnd v d d 9h 9 v d d d gnd v d d d gnd ah 10 v d d d gnd v d d v d d bh 11 v d d v d d d gnd d gnd ch 12 v d d v d d d gnd v d d dh 13 v d d v d d v d d d gnd eh 14 v d d v d d v d d v d d fh 15 table 4. chip address a3?0 pin programming output address bit b3 (msb) b2 b1 b0 (lsb) selected output 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 5. output selection programming
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 19 sclk a0?3 chip address 4 4 a s mode mode mode aout dout b data routing gate 16-bit individual output address mode register 96-bit complete matrix mode register 96-bit parallel latch switch decode switch matrix output enable output address decode mode ce sclk mode din ce 10 10 1 7 7 96 96 96 update en 256 16 figure 3. serial interface block diagram input address bit b3 (msb) b2 b1 b0 (lsb) selected input 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 6. input selection programming bit name function 5 (msb) output enable enable bit for output, 0 = disable, 1 = enable 4 gain set gain select for output buffer, 0 = gain of +1v/v, 1 = gain of +2v/v 3 input address 3 msb of input channel select address 2 input address 2 1 input address 1 0 (lsb) input address 0 lsb of input channel select address table 7. 6-bit serial control word bit assignments (mode 1: complete matrix mode)
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 20 ______________________________________________________________________________________ 0 0 out0 out1 out2 update 1 mode 1 most-significant output buffer control bits are shifted in first, i.e., out15, then out14, etc. last 6 bits shifted in prior to update negative edge program out0. din 6-bit control word figure 5. mode 1: complete matrix mode programming sclk t mnlck t sudi t hddi t pddo t suhud t mnlud next control word t mnhck update dout example of 6-bit serial control word for output control 16 x 16 crosspoint = 6-bit control word sclk din output (i) enabled, a v = +1v/v, connected to input 14 output enabled input address 3 (msb) = 1 input address 2 = 1 input address 1 = 1 input address 0 (lsb) = 0 gain set = +1v/v din figure 4. 6-bit control word and programming example (mode 1: complete matrix mode programming)
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 21 reset the MAX9675 features an asynchronous bidirectional reset with an internal 20k pullup resistor to v dd . when reset is pulled low, either by internal circuitry, or driven externally, the analog output buffers are latched into a high-impedance state. after reset is released, the output buffers remain disabled. the out- puts may be enabled by sending a new 96-bit data word or a 16-bit individual output address word. a reset is initiated from any of three sources. reset can be driven low by external circuitry to initiate a reset, or reset can be pulled low by internal circuitry during power-up (power-on reset) or thermal shutdown. since driving reset low only clears the output buffer enable bit in the matrix control latches, reset can be used to disable all outputs simultaneously. if no new data has been loaded into the 96-bit complete matrix mode register, a single update restores the previous matrix control settings. power-on reset the power-on reset ensures all output buffers are in a disabled state when power is initially applied. a v dd voltage comparator generates the power-on reset. when the voltage at v dd is less than 2.5v, the power- on-reset comparator pulls reset low through internal circuitry. as the digital supply voltage ramps up cross- ing 2.5v, the MAX9675 holds reset low for 40ns (typ). connecting a small capacitor from reset to dgnd extends the power-on-reset delay. see the reset delay vs. reset capacitance graph in the typical operating characteristics. thermal shutdown the MAX9675 features thermal shutdown protection with temperature hysteresis. when the die temperature exceeds +150?, the MAX9675 pulls reset low, dis- abling the output buffers. when the die cools by 20?, the reset pulldown is deasserted, and output buffers remain disabled until the device is programmed again. applications information building large video-switching systems the MAX9675 can be easily used to create larger switching matrices. the number of ics required to implement the matrix is a function of the number of input channels, the number of outputs required, and whether the array needs to be nonblocking. the most straightforward technique for implementing nonblock- ing matrices is to arrange the building blocks in a grid. the inputs connect to each vertical bank of devices in parallel with the other banks. the outputs of each build- ing block in a vertical column connect together in a wired-or configuration. figure 6 shows a 128-input, 32-output, nonblocking array using the MAX9675 16 x 16 crosspoint devices. the wired-or connection of the outputs shown in the diagram is possible because the outputs of the ic devices can be placed in a disabled or high-imped- ance output state. this disable state of the output buffers is designed for a maximum impedance vs. fre- quency while maintaining a low-output capacitance. these characteristics minimize the adverse loading effects from the disabled outputs. larger arrays are constructed by extending this connection technique to more devices. driving a capacitive load figure 6 shows an implementation requiring many out- puts to be wired together. this creates a situation where each output buffer sees not only the normal load impedance, but also the disabled impedance of all the other outputs. this impedance has a resistive and a capacitive component. the resistive components reduce the total effective load for the driving output. total capacitance is the sum of the capacitance of all the disabled outputs and is a function of the size of the matrix. also, as the size of the matrix increases, the length of the pcb traces increases, adding more capacitance. the output buffers have been designed to drive more than 30pf of capacitance while still main- taining a good ac response. depending on the size of the array, the capacitance seen by the output can exceed this amount. there are several ways to improve the situation. the first is to use more building-block crosspoint devices to reduce the number of outputs that need to be wired together (figure 7). in figure 7, the additional devices are placed in a sec- ond bank to multiplex the signals. this reduces the number of wired-or connections. another solution is to put a small resistor in series with the output before the capacitive load to limit excessive ringing and oscilla- tions. figure 8 shows the graph of the optimal isolation resistor vs. capacitive load. a lowpass filter is created from the series resistor and parasitic capacitance to ground. a single r-c does not affect the performance at video frequencies, but in a very large system there may be many r-cs cascaded in series. the cumulative effect is a slight rolling off of the high frequencies caus- ing a "softening" of the picture. there are two solutions to achieve higher performance. one way is to design the pcb traces associated with the outputs such that they exhibit some inductance. by routing the traces in a repeating "s" configuration, the traces that are nearest each other exhibit a mutual inductance increasing the total inductance. this series inductance causes the
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 22 ______________________________________________________________________________________ amplitude response to increase or peak at higher fre- quencies, offsetting the rolloff from the parasitic capaci- tance. another solution is to add a small-value inductor to the output. crosstalk signal and board routing issues improper signal routing causes performance problems such as crosstalk. the MAX9675 has a typical crosstalk rejection of -62db at 6mhz. a bad pcb layout degrades the crosstalk rejection by 20db or more. to achieve the best crosstalk performance: 1) place ground isolation between long critical sig- nal pcb trace runs. these traces act as a shield to potential interfering signals. crosstalk can be degraded by parallel traces as well as directly above and below on adjoining pcb layers. 2) maintain controlled-impedance traces. design as many of the pcb traces as possible to be 75 trans- mission lines. this lowers the impedance of the traces, reducing a potential source of crosstalk. more power is dissipated due to the output buffer driving a lower impedance. 3) minimize ground-current interaction by using a good ground plane strategy. in addition to crosstalk, another key issue of concern is isolation. isolation is the rejection of undesirable feed- through from input to output with the output disabled. the MAX9675 achieves a -110db isolation at 6mhz by selecting the pinout configuration such that the inputs and outputs are on opposite sides of the package. coupling through the power supply is a function of the quality and location of the supply bypassing. use appropriate low-impedance components and locate them as close as possible to the ic. avoid routing the inputs near the outputs. power-supply bypassing the MAX9675 operates from a ?v supply. for dual- supply operation, bypass all supply pins to ground with 0.1? capacitors. figure 7. 64 x 16 nonblocking matrix with reduced capacitive loading in (0?5) in (16?1) in (32?7) in (48?3) outputs (0?5) outputs (16?2) 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out in (64?9) in (80 95) in (96?11) in (112?27) MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 figure 6. 128 x 32 nonblocking matrix using 16 x 16 crosspoint devices in (0?5) in (16?1) in (32?7) in (48?3) outputs (0?5) 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out 16 in 16 out MAX9675 MAX9675 MAX9675 MAX9675 MAX9675 16 in 16 out MAX9675
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 23 driving a pcb interconnect or a cable (a v = +1v/v or +2v/v) the MAX9675 output buffers can be programmed to either a v = +1v/v or +2v/v. the +1v/v configuration is typically used when driving a short-length (less than 3cm), high-impedance ?ocal?pcb trace. to drive a cable or a 75 transmission line trace, program the gain of the output buffer to +2v/v and place a 75 resistor in series with the output. the series termination resistor and the 75 load impedance act as a voltage- divider that divides the video signal in half. set the gain to +2v/v to transmit a standard 1v video signal down a cable. the series 75 resistor is called the back-match, reverse termination, or series termination. this 75 resistor reduces reflections, and provides isolation, increasing the output-capacitive-driving capability. matrix programming the MAX9675? unique digital interface simplifies pro- gramming multiple MAX9675 devices in an array. multiple devices are connected with dout of the first device connecting to din of the second device, and so on (figure 9). two distinct programming modes, indi- vidual output address mode (mode = 0) and complete matrix mode (mode = 1), are selected by toggling a single mode control pin high or low. both modes oper- ate with the same physical board layout. this allows ini- tial programming of the ic by daisy-chaining and sending one long data word while still being able to address immediately and update individual locations in the matrix. individual output address mode (mode 0) in individual output address mode, the devices are connected in a serial bus configuration, with the data routing gate (figure 3) connecting din to dout, mak- ing each device a virtual node on the serial bus. a sin- gle 16-bit control word is sent to all devices simultaneously. only the device with the corresponding chip address responds to the programming word, and updates its output. in this mode, the chip address is set through hardware pin strapping of a3?0. the host then communicates with the device by sending a 16-bit word consisting of 2 don? care msb bits, 4 chip address bits, and 10 bits of data to make the word exactly 2 bytes in length. the 10 data bits are broken down into 4 bits to select the output to be programmed; 1 bit to set the output enable; 1 bit to set gain; and 4 bits to select the input to be connected to that output. in this method, the matrix is programmed one output at a time. complete matrix mode (mode 1) in complete matrix mode, the devices are connected in a daisy-chain fashion where n x 96 bits are sent to pro- gram the entire matrix, and where n = the number of MAX9675 devices connected in series. this long data word is structured such that the first bit is the lsb of the last device in the chain and the last data bit is the msb of the first device in the chain. the total length of the data word is equal to the number of crosspoint devices to be programmed in series times 96 bits per crosspoint device. this programming method is most often used at startup to initially configure the switching matrix. 0 10 5 20 15 25 30 0 500 optimal isolation resistance vs. capacitive load capacitive load (pf) isolation resistance ( ) 200 100 300 400 figure 8. optimal isolation resistor vs. capacitive load
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 24 ______________________________________________________________________________________ host controller din sclk ce mode update dout chip address = 0 chip address = 1 virtual serial bus (mode 0: individual output address mode) chip address = 2 a3 a2 a1 a0 MAX9675 din sclk ce mode update dout a3 v dd a2 a1 a0 MAX9675 din sclk ce mode update dout next device a3 a2 a1 a0 MAX9675 v dd figure 9. matrix mode programming chip information transistor count: 24,467 process: bicmos
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain ______________________________________________________________________________________ 25 top view MAX9675 tqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 in4 agnd in5 agnd in6 agnd in7 agnd in8 agnd in9 agnd in10 agnd in11 agnd in12 a3 in13 a2 in14 a1 in15 a0 v cc v cc out2 v ee out3 v cc out4 v ee out5 v cc out6 v ee out7 v cc out8 v ee out9 v cc out10 v ee out11 v cc out12 v ee out13 v cc 26 27 28 29 30 n.c. n.c. dout dgnd aout sclk ce mode reset update din v dd n.c. n.c. n.c. n.c. n.c. n.c. n.c. agnd agnd v cc out15 v ee out14 n.c. n.c. v ee agnd in3 agnd in2 agnd in1 agnd in0 n.c. n.c. n.c. n.c. n.c. agnd agnd agnd v cc out0 v ee out1 n.c. n.c. + pin configuration
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain 26 ______________________________________________________________________________________ package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . 100l,tqfp.eps package outline 21-0085 2 1 b 100l tqfp, 14x14x1.0mm
MAX9675 110mhz, 16 x 16 video crosspoint switch with programmable gain maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. package outline, 21-0085 2 2 b 100l tqfp, 14x14x1.0mm package information (continued) for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 100 tqfp c100-1 21-0085

▲Up To Search▲

Price & Availability of MAX9675

	To Download MAX9675 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .